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SY89112U 2.5/3.3v low jitt er, low skew 1:12 lvpecl fanout buffer with 2:1 input mux and internal termination february 2005 m9999-022405 hbwhelp@micrel.com or (408) 955-1690 precision edge is a register ed trademark of micrel, inc micro leadframe is a trademark of amkor technology, inc. general description the SY89112U is a low jitter, low skew, high-speed lvpecl 1:12 differential f anout buffer optimized for precision telecom and enterprise server distribution applications. the input includes a 2:1 mux for clock switchover application. unli ke other multiplexers, this input includes a unique isolation design to minimize channel-to-channel crosstalk. the SY89112U distributes clock frequencies from dc to >2ghz guaranteed over temperat ure and voltage. the SY89112U incorporates a synchronous output enable (en) so that the outputs will only be enabled/disabled when they are already in the low state. this reduces the chance of generating ?runt? clock pulses. the SY89112U differential input includes micrel?s unique, patent-pending 3-pin input termination architecture that directly interfaces to any differential signal (ac- or dc-coupled) as small as 100mv (200mv pp ) without any level shifting or termination resistor networks in the signal path. for ac-coupled input interface, an on-board output reference voltage (vref-ac) is provided to bi as the center-tap (vt) pin. the outputs are 800mv, 100k-compatible lvpecl with fast rise/fall times guaranteed to be less than 220ps. the SY89112U operates from a 2.5v 5% or 3.3v 10% supply and is guaranteed over the full industrial temperature range of ?40c to +85c. the SY89112U is part of micrel?s high-speed, precision edge ? product line. all support documentation can be found on micrel?s web site at www.micrel.com . precision edge ? features ? selects between 1 of 2 inputs, and provides 12 precision, low skew lvpecl output copies ? guaranteed ac performance over temperature and voltage: ? dc to >2ghz throughput ? <550ps propagation delay clk-to-q ? <220ps rise/fall time ? <25ps output-to-output skew ? ultra-low jitter design: ? <1ps (rms) random jitter ? <10ps (pp) total jitter (clock) ? <1ps (rms) cycle-to-cycle jitter ? <0.7ps (rms) crosstalk induced jitter ? unique, patent-pending input termination and vt pin accepts dc-coupled and ac-coupled differential inputs ? unique, patent-pending 2:1 input mux provides superior isolation to minimize channel-to-channel crosstalk ? 800mv, 100k lvpecl output swing ? power supply 2.5v + 5% or 3.3v + 10% ? industrial temperature range ?40c to +85c ? available in 44-pin (7mm x 7mm) mlf? package applications ? multi-processor server ? sonet/sdh clock/data distribution ? fibre channel distribution ? gigabit ethernet clock distribution
micrel, inc. SY89112U february 2005 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 2 functional block diagram
micrel, inc. SY89112U february 2005 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 3 ordering information (1) part number package type operating range package marking lead finish SY89112Umg mlf-44 industrial SY89112U with pb-free bar-line indicator nipdau pb-free SY89112Umgtr (2) mlf-44 industrial SY89112U with pb-free bar-line indicator nipdau pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 44-pin mlf tm (mlf-44)
micrel, inc. SY89112U february 2005 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 4 pin description pin number pin name pin function 2, 5 7, 10 clk0, /clk0 clk1, /clk1 differential inputs: these input pairs are the differential signal inputs to the device. inputs accept ac- or dc-coup led differential signals as small as 100mv. each pin of a pair internally terminates to a vt pin through 50 ? . note that these inputs will default to an in determinate state if left open. please refer to the ?input interface applications? section for more details. 3, 8 vt0, vt1 input termination center-tap: each side of the differential input pair terminates to a vt pin. the vt pins provide a center-tap to a termination network for maximum interface flexibility. see ?input in terface applications? section for more details. 4 9 vref-ac0 vref-ac1 reference voltage: these outputs bias to v cc ?1.2v. they are used when ac coupling the inputs (clk, /clk). for ac-coupled applications, connect v ref-ac to the vt pin and bypass with a 0.01 f low esr capacitor to v cc . see ?input interface applications? section for more details. maximum sink/source current is 1.5ma. due to the limited drive capability, each vref-ac pin is only intended to drive its respective vt pin. 44 clk_sel this single-ended ttl/cmos-compatible input selects the inputs to the multiplexer. note that this input is internally connected to a 25k ? pull-up resistor and will default to a logic high state if left open. 12 en this single-ended ttl/cmos-compatible input functions as a synchronous output enable. the synchronous enable en sures that enable/disable will only occur when the outputs are in a logic low state. note that this input is internally connected to a 25k ? pull-up resistor and will default to logic high state (enabled) if left open. 13,22,23,28, 33,34,43 vcc positive power supply. bypass with 0.1 f//0.01 f low esr capacitors and place as close to each vcc pin as possible. 42, 41 40, 39 38, 37 36, 35 32, 31 30, 29 27, 26 25, 24 21, 20 19, 18 17, 16 15, 14 q0, /q0 q1, /q1 q2, /q2 q3, /q3 q4, /q4 q5, /q5 q6, /q6 q7, /q7 q8, /q8 q9, /q9 q10, /q10 q11, /q11 differential 100k lvpecl outputs: thes e lvpecl outputs are the precision, low skew copies of the inputs. please re fer to the truth table below for details. unused output pairs may be left open. terminate with 50 ? to v cc ?2v. see ?lvpecl output interface applicati ons? section for more details. 1, 6, 11 gnd, exposed pad ground. gnd pins and exposed pad must both be connected to the most negative potential of chip the ground. truth table en clk_sel q /q h l clk0 /clk0 h h clk1 /clk1 l x l (1) h (1) note: 1. transition occurs on next negative transition of the non-inverted input.
micrel, inc. SY89112U february 2005 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 5 absolute maximum ratings (1) supply voltage (v cc ) ..........................?0.5v to +4.0v input voltage (v in ) ..................................?0.5v to v cc lvpecl output current (i out ) continuous ................................................. 50ma surge ........................................................ 100ma termination current source or sink current on vt ................. 100ma input current source or sink current on clk, /clk....... 50ma v ref-ac current source or sink current ................................ 2ma lead temperature (solderi ng, 20 sec.) ..........+260c storage temperature (t s )..................?65c to 150c operating ratings (2) supply voltage (v cc ).................. +2.375v to +2.625v ......................................................+3.0v to +3.6v ambient temperature (t a )................ ?40c to +85c package thermal resistance (3) mlf? ( ja ) still-air ..................................................... 42c/w mlf? ( jb ) junction-to-board .................................... 20c/w dc electrical characteristics (4) t a = ?40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v cc power supply 2.375 3.0 2.625 3.6 v v i cc power supply current no load, max. v cc 95 130 ma r in input resistance (in-to-vt) 45 50 55 ? r diff_in differential input resistance (in-to-/in) 90 100 110 ? v ih input high voltage (in, /in) 1.2 v cc v v il input low voltage (in, /in) 0 v ih ?0.1 v v in input voltage swing (in, /in) see figure 1a. 0.1 1.7 v v diff_in differential input voltage swing |in?/in| see figure 1b. 0.2 v v t_in in-to-vt (in, /in) 1.28 v v ref-ac output reference voltage v cc ?1.3 v cc ?1.2 v cc ?1.1 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those detailed in the operat ional sections of this data s heet. exposure to absolute maximu m ratings conditions for extended periods ma y affect device reliability. 2. the data sheet limits are not guaranteed if t he device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (o r equivalent) to the devices most negative potential on the pcb . ja and jb values are determined for a 4-layer board in still-air, unless otherwise stated. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d.
micrel, inc. SY89112U february 2005 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 6 lvpecl outputs dc elect rical characteristics (5) v cc = +2.5v 5% or +3.3v 10%; t a = ?40c to +85c; r l = 50 ? to v cc ? 2v, unless otherwise stated. symbol parameter condition min typ max units v oh output high voltage q, /q v cc ?1.145 v cc ?0.895 v v ol output low voltage q, /q v cc ?1.945 v cc ?1.695 v v out output voltage swing q, /q see figure 1a 550 800 mv v diff-out differential output voltage swing q, /q see figure 1b 1100 1600 mv lvttl/cmos dc electri cal characteristics (5) v cc = +2.5v 5% or +3.3v 10%; t a = ?40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v cc v v il input low voltage 0.8 v i ih input high current ?125 30 a i il input low current ?300 a note: 5. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d.
micrel, inc. SY89112U february 2005 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 7 ac electrical characteristics (6) v cc = +2.5v 5% or +3.3v 10%; t a = ?40c to + 85c, r l = 50 ? to v cc ? 2v, unless otherwise stated. symbol parameter condition min typ max units f max maximum operating frequency v out 400mv 2 3 ghz propagation delay clk to q v in 100mv 300 400 550 ps t pd propagation delay clk_sel to q 200 350 600 ps t pd tempco differential propagation delay temperature coefficient 150 fs/ o c t s set-up time en-to-clk note 7 0 ps t h hold time clk-to-en note 7 500 ps t skew output-to-output skew part-to-part skew note 8 note 9 25 200 ps cycle-to-cycle jitter note 10 1 ps (rms) random jitter (rj) note 11 1 ps (rms) total jitter (tj) note 12 10 ps (pp) t jitter adjacent channel crosstalk-induced jitter note 13 0.7 ps (rms) t r, t f output rise/fall time (20% to 80%) at full output swing. 70 140 220 ps notes: 6. high-frequency ac-parameters are guar anteed by design and characterization. 7. set-up and hold times apply to synchronous applications that in tend to enable/disable before the next clock cycle. for async hronous applications, set-up and hold do not apply. 8. output-to-output skew is measured between two di fferent outputs under ident ical input transitions. 9. part-to-part skew is defined for two parts with identical pow er supply voltages at the same temperature and with no skew of the edges at the respective inputs 10. cycle-to-cycle jitter definition: the va riation of periods between adjacent cycles, t n ? t n-1 where t is the time between rising edges of the output signal. 11. random jitter is measured with a k 28.7 character pattern, measured at micrel, inc. SY89112U february 2005 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 8 operating characteristics v cc = +3.3v, gnd = 0, v in = 100mv, r l = 50 ? to v cc ?2v, t a = 25c, unless otherwise stated.
micrel, inc. SY89112U february 2005 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 9 functional characteristics v cc = +3.3v, gnd = 0, v in = 100mv, r l = 50 ? to v cc ?2v, t a = 25c, unless otherwise stated.
micrel, inc. SY89112U february 2005 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 10 singled-ended and differential swings figure 1a. singled-ended voltage swing figure1b. differential voltage swing timing diagrams t pd ? differential in-to-differential out t pd ? clk_sel-to-differential out t pd ? set-up and hold time en-to-differential in 800 mv (typical) v in , v out v diff_in , v diff_out 1600 mv (typical) /clk clk /q q t pd clk_sel /q q t pd t pd ~ ~ ~ ~ ~ ~ v cc /2 v cc /2 /clk clk /q q t s en t h v cc /2 v cc /2
micrel, inc. SY89112U february 2005 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 11 input and output stages figure 2a. simplified differential input stage figure 2b. simplified lvpecl output stage input interface applications figure 3a. lvpecl interface (dc-coupled) figure 3b. lvpecl interface (ac-coupled) option: may connect v t to v cc figure 3c. cml interface (dc-coupled) figure 3d. cml interface (ac-coupled) figure 3e. lvds interface
micrel, inc. SY89112U february 2005 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 12 lvpecl output inte rface applications lvpecl has high input impeda nce, very low output (open emitter) impedance, and small signal swing, which result in low emi. l vpecl is ideal for driving 50 ? and 100 ? controlled impedance transmission lines. there are several techniques for terminating the lvpecl output: parallel termination-thevenin equivalent, parallel termination (3-resistor), and ac-coupled termination. unused output pairs may be left floating. however, single-ended outputs must be terminated, or balanced. figure 4a. parallel thevenin-equivalent termination figure 4b. parallel termination (3-resistor) related product and su pport documentation part number function data sheet link sy89113u 2.5/3.3v low jitter, low skew 1:12 lvds fanout buffer with 2:1 input mux and internal termination http://www.micrel.com/product-info/products/sy89113u.shtml hbw solutions new products and applications www.micrel.com/product-info/products/solutions.shtml mlf tm application note www.amkor.com/p roducts/notes_papers/mlfappnote.pdf
micrel, inc. SY89112U february 2005 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 13 44 lead micro leadframe tm (mlf-44) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specificati ons at any time without notification to the customer. micrel products are not designed or authoriz ed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems ar e devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to r esult in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or sys tems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, incorporated.

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